When you say sequential integer operations, do you mean integer operations that really are sequential? In other words, the instructions can't be performed in parallel because of data dependencies? If not, then this is already possible with a sufficiently wide superscalar processor or really big SIMD units. But let's assume you really mean sequential integer operations. The only pipeline stage in this example that can't work on several instructions at once is the execute stage, so I'm assuming that's where the bottleneck is here. This means that the speed is limited by the clock frequency. So, here are two ways to achieve your prediction: 1. Crank up the clock! Find a way to get it up to 12 GHz without burning up. 2. Make the execute stage capable of running much faster than the rest of the processor does. This is natural for asynchronous processors; in normal operation the integer functional units will be sitting idle most of the time waiting for input, and the bulk of the time and complexity will be in fetching the instructions, decoding them, scheduling them, and in memory access and I/O. But in your contrived scenario, the integer math units could just go hog wild and the rest of the processor would keep them fed. This can be done with current semiconductor technology, I'm pretty sure. So, either way, kind of an ambitious prediction. I like it.