Electronic NAND gates have a nonzero time delay. This allows you to connect them in cyclic graphs to implement loops.

You can model such a circuit using a set of logical fomulae that has one logical NAND per gate per timestep. Ata pointed out that you need an infinitely large set of logical formulae if you want to model an arbitrarily long computation this way. Though you can compress it back down to a finite description if you're willing to extend the notation a bit, so you might not consider that a problem.